Machine-written · ai
Intel CTO: frontier wafer capacity may only double as AI compute hits ceiling
Intel Chief Technology Officer Pushkar Ranade told a podcast that leading-edge wafer output cannot grow tenfold even with ample funding, and that a doubling is a more realistic limit. He linked the ceiling to the semiconductor supply chain's coordinated expansion.

Intel CTO Pushkar Ranade said in a Dwarkesh podcast interview that even with sufficient funding, global leading-edge wafer output cannot be expanded tenfold, and a doubling is a more realistic upper limit, IT之家 reported.
Asked whether the world has enough tools to raise frontier wafer production by 10 times, he replied that the increase would not be tenfold but might be about double. He said the limit comes from the entire semiconductor supply chain's ability to expand in a coordinated way, rather than from any single link.
IT之家, citing a blog post, said Ranade noted that AI computing power has grown roughly three times per year over the past decade, but key equipment, clean rooms and fab scale needed for advanced chips are becoming a new capacity ceiling.
ASML makes fewer than 100 EUV lithography machines per year and is unlikely to expand that much by the end of the decade, while Intel, TSMC and memory makers such as SK Hynix compete for these tools.
Ranade explained that equipment ordered today typically arrives about 18 months later, meaning capacity may land only around 2028. New fabs also do not automatically produce more wafers because equipment supply cannot keep up.
To raise overall output, equipment suppliers, their upstream suppliers and deeper sub-suppliers would all need to add capacity at the same time, and bottlenecks in lithography machines, key components, materials, inspection equipment or fab construction could prevent a large jump in advanced wafer output.